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Wenjie Xiong

I will join ECE at Virginia Tech in Jan 2022. I am currently a postdoctoral researcher at Facebook AI Research (FAIR). Previously, I earned my Ph.D. at Yale University, working with Prof. Jakub Szefer

My research interests are in hardware security, where I leverage hardware features to enhance the security of computer systems as well as identify and mitigate security vulnerabilities that are rooted in hardware design. I am passionated about leveraging hardware to build secure systems.

News

04/2021: Our paper “Leaking Information Through Cache LRU States” is selected as the Featured Paper in the April 2021 issue of IEEE Transactions on Computers (TC)! check out the talk.

03/2021: I am organizing Secure and Private Systems for Machine Learning Workshop (SPSL2021).

01/2021: Our paper “Leaking Information Through Cache LRU States in Commercial Processors and Secure Caches” is accepted to IEEE Transactions on Computers.

01/2021: Our paper “Leaking Information Through Cache LRU States” is selected as an Honorable Mention of IEEE Micro Top Picks 2021!

12/2020: Our paper “Survey of Transient Execution Attacks” is accepted to ACM Computing Surveys!

Research

Efficient Hardware Designs with Built-in Security
Why security and privacy?

We are living in an increasingly connected world where an unprecedented amount of data are being collected, transferred, and processed across tens of billions of connected devices and systems daily, including private user information or company intellectual properties (IPs). In addition to the pursuit of better performance and lower energy, guaranteeing security and privacy is now considered a first-class citizen in architecting and designing future computing systems. 

Why hardware security?

Foundation of security: Hardware is the bottom layer of the computation stack. Hardware vulnerabilities will compromise the whole system and can hardly be mitigated by software efficiently.

Efficient security solution: Hardware-software co-design for security can yield efficient solutions.

Physical features for security: Hardware is the interface between software and the physical world. The physical and analog features of hardware can be leveraged for security.

How do we pursue hardware security?

We conduct research in the intersection of computer architecture, circuits, cryptography, formal methods, and machine learning. Our goal is to deliver efficient hardware designs with built-in security.

 

Research Projects

Secure Heterogeneous Architectures
It is a trend to include several different computing modules, such as GPU, FPGA, ASIC accelerators, memory, etc., to a computing platform for high-performance computing. The heterogeneous architectures face new security challenges to protect data across different modules. New designs are needed to protect data end-to-end.
 
Related Publication:

“WiP: Near-Data Processing over Ciphertext” Wenjie Xiong, Liu Ke, Peter Tang, Edward Suh, Xuan Zhang, Hsien-Hsin S. Lee. IEEE International Symposium on Secure and Private Execution Environment Design (SEED), Sep. 2021

Side and Covert Channel Attacks and Mitigations in Processors
Nowadays, hardware is usually reused for different applications or users. For example, many applications are running on one device, multiple talents may share the same server on the cloud, etc. Sharing of hardware lead to potential side and covert-channel attacks that lead to information leakage. It is a challenge to understand how these attacks happen and how to mitigate them.
 
Selected Publications:
“Leaking Information Through Cache LRU States”, Wenjie Xiong, and Jakub Szefer, in Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA), February 2020. 
“A Benchmark Suite for Evaluating Caches’ Vulnerability to Timing Attacks”, Shuwen Deng, Wenjie Xiong, and Jakub Szefer, in Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2020.
“Secure TLBs”, Shuwen Deng, Wenjie Xiong, and Jakub Szefer, in Proceedings of the International Symposium on Computer Architecture (ISCA), June 2019.
 
Device Authentication and Software Protection Leveraging Hardware Features
Hardware has physical and analog features that can be leveraged for security purpose. In our DRAM PUFs project, we leverage the DRAM retention error for device authentication, fingerprinting, key storage, and software protection.
 
Selected Publications:
“Run-time Accessible DRAM PUFs in Commodity Devices”, Wenjie Xiong, André Schaller, Nikolaos A. Anagnostopoulos, Muhammad Umair Saleem, Sebastian Gabmeyer, Stefan Katzenbeisser, and Jakub Szefer, in Proceedings of the Conference on Cryptographic Hardware and Embedded Systems (CHES), August 2016.
“Intrinsic Rowhammer PUFs: Leveraging the Rowhammer Effect for Improved Security”, André Schaller, Wenjie Xiong, Muhammad Umair Saleem, Nikolaos A. Anagnostopoulos, Stefan Katzenbeisser, and Jakub Szefer, in Proceedings of the International Symposium on Hardware Oriented Security and Trust (HOST), May 2017. 
“Spying on Temperature using DRAM”, Wenjie Xiong, Nikolaos Athanasios Anagnostopoulos, André Schaller, Stefan Katzenbeisser, and Jakub Szefer, in Proceedings of the Design, Automation, and Test in Europe (DATE), March 2019.
“Software Protection using Dynamic PUFs”, Wenjie Xiong, André Schaller, Stefan Katzenbeisser, and Jakub Szefer, in IEEE Transactions on Information Forensics and Security (TIFS), vol. 15, pp. 2053-2068, 2020.

 

Publications

Google Scholar · dblp CS Bibliography · ResearchGate

 

Peer-reviewed Publications

  • Wenjie Xiong, André Schaller, Nikolaos A. Anagnostopoulos, Muhammad Umair Saleem, Sebastian Gabmeyer, Stefan Katzenbeisser, and Jakub Szefer, “DRAM PUFs in Commodity Devices”, in HW-Security TopPicks issue of IEEE Design & Test, vol. 38, no. 3, pp. 76-83, June 2021. [ paper ]
  • Shuwen Deng, Wenjie Xiong, and Jakub Szefer, “Understanding Insecurity of Processor Caches due to Cache Timing-Based Vulnerabilities”, in IEEE Security & Privacy,  vol. 19, no. 3, pp. 42-49, May-June 2021. paper ]

  • Wenjie Xiong, and Jakub Szefer, “Survey of Transient Execution Attacks and their Mitigations”, in ACM Computing Surveys, vol. 54, no. 3, Article 54, May 2021. [ paper ] [ BibTeX ]  [ arXiv ]

  • Shanquan Tian, Ilias Giechaskiel, Wenjie Xiong, and Jakub Szefer, “Cloud FPGA Cartography using PCIe Contention”, in Proceedings of the International Symposium on Field-Programmable Custom Computing Machines (FCCM), May 2021. [ paper ] [ BibTeX ] 
  • Wenjie Xiong, Stefan Katzenbeisser, and Jakub Szefer, “Leaking Information Through Cache LRU States in Commercial Processors and Secure Caches”, in IEEE Transactions on Computers, vol. 70, no. 04, pp. 511-523, 2021. Featured Paper in the April 2021 issue of IEEE Transactions on Computers (TC) paper ] [ BibTeX ]  [ Video ] [ Video (in Chinese) ]
  • Shuwen Deng, Wenjie Xiong, and Jakub Szefer, “A Benchmark Suite for Evaluating Caches’ Vulnerability to Timing Attacks”, in Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2020.  [ PDF ]  [ BibTeX ]  [ CODE ] 
  • Shanquan Tian, Wenjie Xiong, Ilias Giechaskiel, Kasper Rasmussen, and Jakub Szefer, “Fingerprinting Cloud FPGA Infrastructures”, in Proceedings of the International Symposium on Field-Programmable Gate Arrays (FPGA), February 2020. [ PDF ]  [ BibTeX ]  [ CODE ] 
  • Wenjie Xiong, and Jakub Szefer, “Leaking Information Through Cache LRU States”, in Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA), February 2020. (IEEE Micro Top Picks 2021 Honorable Mention) PDF ]  [ BibTeX ]  [ arXiv ]  [ Lightning Talk ]  [ CODE ] 
  • Wenjie Xiong, André Schaller, Stefan Katzenbeisser, and Jakub Szefer, “Software Protection using Dynamic PUFs”, in IEEE Transactions on Information Forensics and Security (TIFS), vol. 15, pp. 2053-2068, 2020. [ PDF ]   [ BibTeX ]  [ CODE ] 
  • Shuwen Deng, Wenjie Xiong, and Jakub Szefer, “Analysis of Secure Caches using a Three-Step Model for Timing-Based Attacks”, in Journal of Hardware and Systems Security (HASS), vol. 3, no. 4, pp.397-425, December 2019. [ PDF ]  [ BibTeX ] 
  • Shuai Chen, Wenjie Xiong, Yehan Xu, Bing Li, and Jakub Szefer, “Thermal Covert Channels Leveraging Package-On-Package DRAM”, in Proceedings of the International Conference on Trust, Security and Privacy in Computing and Communications (TrustCom), August 2019. [ PDF ]  [ BibTeX ] 
  • Shuwen Deng, Wenjie Xiong, and Jakub Szefer, “Secure TLBs”, in Proceedings of the International Symposium on Computer Architecture (ISCA), June 2019. [ PDF ]  [ BibTeX ] 
  • Shuwen Deng, Doğuhan Gümüşoğlu, Wenjie Xiong, Y. Serhan Gener, Onur Demir, and Jakub Szefer, “SecChisel Framework for Security Verification of Secure Processor 
Architectures”, in Proceedings of the Workshop on Hardware and Architectural Support for Security and Privacy (HASP), June 2019. [ PDF ]  [ BibTeX ] 
  • Wenjie Xiong, André Schaller, Stefan Katzenbeisser, and Jakub Szefer, “Dynamic Physically Unclonable Functions”, in Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI), May 2019. [ PDF ]  [ BibTeX ] 
  • Wenjie Xiong, Nikolaos Athanasios Anagnostopoulos, André Schaller, Stefan Katzenbeisser, and Jakub Szefer, “Spying on Temperature using DRAM”, in Proceedings of the Design, Automation, and Test in Europe (DATE), March 2019. [ PDF ]  [ BibTeX ] [ CODE ]
  • Nikolaos Athanasios Anagnostopoulos, Tolga Arul, Yufan Fan, Christian Hatzfeld, André Schaller, Wenjie Xiong, Manishkumar Jain, Muhammad Umair Saleem, Jan Lotichius, Sebastian Gabmeyer, Jakub Szefer, and Stefan Katzenbeisser, “Intrinsic Run-Time Row Hammer PUFs: Leveraging the Row Hammer Effect for Run-Time Cryptography and Improved Security”, in Cryptography, vol. 2, no. 3, June 2018. [ PDF ]  [ BibTeX ] 
  • Shuwen Deng, Wenjie Xiong, and Jakub Szefer, “Cache Timing Side-Channel Vulnerability Checking with Computation Tree Logic”, in Proceedings of the Workshop on Hardware and Architectural Support for Security and Privacy (HASP), June 2018. [ PDF ]  [ BibTeX ] 
  • André Schaller†, Wenjie Xiong†, Nikolaos Athanasios Anagnostopoulos, Muhammad Umair Saleem, Sebastian Gabmeyer, Boris Skoric, Stefan Katzenbeisser and Jakub Szefer, “Decay-Based DRAM PUFs in Commodity Devices”, in IEEE Transactions on Dependable and Secure Computing (TDSC), vol. 16, issue 3, pp.462-475, May-June 1 2019. † The first two authors contributed equally. [ PDF ] [ BibTeX ]
  • André Schaller, Wenjie Xiong, Muhammad Umair Saleem, Nikolaos A. Anagnostopoulos, Stefan Katzenbeisser, and Jakub Szefer, “Intrinsic Rowhammer PUFs: Leveraging the Rowhammer Effect for Improved Security”, in Proceedings of the International Symposium on Hardware Oriented Security and Trust (HOST), May 2017. (Best Student Paper Finalist) PDF ] [ BibTeX ] [ CODE ]
  • Wenjie Xiong, André Schaller, Nikolaos A. Anagnostopoulos, Muhammad Umair Saleem, Sebastian Gabmeyer, Stefan Katzenbeisser, and Jakub Szefer, “Run-time Accessible DRAM PUFs in Commodity Devices”, in Proceedings of the Conference on Cryptographic Hardware and Embedded Systems (CHES), August 2016. (Top Picks in Hardware and Embedded Security 2019) PDF ] [ BibTeX ] [ CODE ]

Technical Reports

  • Wenjie Xiong, and Jakub Szefer, “Survey of Transient Execution Attacks”, May 2020. [ arXiv ]
  • Onur Demir, Wenjie Xiong, Faisal Zaghloul, and Jakub Szefer, “Survey of Approaches for Security Verification of Hardware/Software Systems”, August 2016. [ ePrint ]

News

  • Wenjie Xiong, and Jakub Szefer, “Memristive fingerprints prove key destruction.”, Nature Electronics 1(10), p.527, 2018.

Services

 

Conference/Workshop Organizing

Session Chair for session 1: “the eternal war of side channels” in the IEEE International Symposium on Secure and Private Execution Environment Design (SEED 2021)

Publications Chair for the IEEE International Symposium on Secure and Private Execution Environment Design (SEED 2021)

Proceedings Chair for the 39th IEEE International Conference on Computer Design (ICCD 2021)

Publicity Chair for the 28th IEEE International Symposium on High-Performance Computer Architecture (HPCA 2022)

Organizing Committee of Secure and Private Systems for machine Learning (SPSL) workshop, co-located with ISCA 2021

Conferences/workshops Program Committees Activities

External PC of Architectural Support for Programming Languages and Operating Systems (ASPLOS 2022)

PC of the 39th IEEE International Conference on Computer Design — Processor Architecture Track (ICCD 2021)

External PC of Architectural Support for Programming Languages and Operating Systems (ASPLOS 2021)

PC of the 9th International Workshop on Hardware and Architectural Support for Security and Privacy (HASP 2020)

PC of the 8th International Workshop on Hardware and Architectural Support for Security and Privacy (HASP 2019)

Journal Reviewing Activities

ACM Computing Surveys (CSUR)

IEEE Computer Architecture Letters (CAL)

Design Automation for Embedded Systems (DAEM)

IEEE Security & Privacy

IEEE Transactions on Circuits and Systems I

IEEE Transactions on Computers (TC)

Advanced Electronic Materials

ACM Transactions on Architecture and Code Optimization (TACO)

IEEE Design & Test

Nature Electronics

IEEE Access

International Journal of Circuit Theory and Applications (CTA)

IEEE Consumer Electronics Magazine

ACM Transactions on Embedded Computing Systems (TECS)

IEEE Transactions on Dependable and Secure Computing (TDSC)

Openings

Getting involved!

We are looking for postdocs, PhDs, Masters, and undergraduates to join us! Please email me.